Skip to main content


Showing posts from February 14, 2021

Featured Post

Resuming Pace: I Shall Not Be Pursuing a Second Bachelor's Degree

On May the 5th, 2021, I used a strong position deciding my pursuit of a second Bachelor’s degree: my choice was the University of Maryland Global Campus (UMGC, link ), but I decided to resume my Master’s program, by itself.  Let me explain with Scripture: the Gospel of Jesus Christ According to Matthew, specifically. In ancient times, records of a man called Jesus the Christ were written. Among these records was a Gospel, According to Matthew, of Jesus Christ. According to legend, Jesus Christ stated, “Blessed are the meek: for they shall inherit the earth (KJV, Matthew 5:5, link ).” Jesus the Christ was saying those who are submissive shall inherit the earth rather than those who are brash.  In my attempt at starting a second Bachelor’s program, I eventually realized I had been too pushy: I wanted the May 19th start date, and I wanted the admission process expedited, I wanted ease of access between majors, I wanted advantages to the application process because of what UMGC (I was gra

On Datapaths: Accepting, but Surpassing Limits

In Computer Organization and Design MIPS Edition, authors, David A. Patterson and John L. Hennessy wrote a piece of information: they defined single-cycle implementation. On single-cycle implementation, Patterson and Hennessy wrote, “Also called single clock cycle implementation. An implementation in which an instruction is executed in one clock cycle. While easy to understand, it is too slow to be practical” (Patterson & Hennessy 2014). Patterson and Hennessy were saying this: for every instruction, an instruction requires one clock cycle. As this is a scalability issue, increasing the instructions to two: requires two clock cycles. Against the pseudo-infinity within, I shall describe, common case hardware, von Neumann computers: this requires a series because this shall make calculation sufficiently easier than a sequence that has no calculation. The series is this: from 0 instructions to n instructions, the series X is incremented one instruction divided the equivalent clock cyc

Data Pipelines and Data Distribution

As the C programming distributive library, MPI (Message Passing Interface), encourages simultaneous application process task because it is efficient enough, our MIPS 5-stage pipeline system allows simultaneous instruction execution. The potential benefit of applying the principles is the sufficient reduction in program execution time. As a major effect, data hazards can occur: when a pipeline changes its read/write accessibility order because the order differ, sequentially; but specifically, on the unpipelined machine, seen regarding sequentially executing instructions[1,2] . Called a data stall because a stall degrades the ideal program performance, the ideal CPI and pipeline stalled-clock cycles per instruction results in a greater than 1 CPI pipelined CPI. For maintaining accurate overhead, cycle time overhead should not be ignored, so pipelining is accurately calculated, but the result will not be an intuitive one. Thankfully, data forwarding can solve data hazards because forwardi

Contact Form


Email *

Message *