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Showing posts from January 17, 2021

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Utilizing Media: A Response to Deepfakes

  Of the ACM (the Association for Computing Machinery), a magazine called Communication of the ACM's edition releases 1 month before its stated release month. In the latest edition, regarding March 2021, of Communications of the ACM , Column Editor, Susan J. Winter wrote Computing Ethics: What To Do About Deepfakes . Regarding Winter’s desire to halt or hinder illegal or unethical deepfakes, a video technology like wearing a full body masking suit, Winter wrote, “Here are three areas where technical experts can make positive contributions to the development of synthetic media technologies: education and media literacy, subject defense, and verification” (Winter, March, 2021). Winter was saying actions such as teaching and having disruptive technology knowledge, researching professionally, and proving concepts are parts of deepfake experts’ calculus. But this much work specializes such that entry level, junior, work will probably be offered to overqualified professionals. Technic

Spectre and Meltdown Explained, and a Proposed Counter Against Them

On January 15, 2018, 2:58 AM PST, Josh Fruhlinger wrote Spectre and Meltdown explained: What they are, how they work, what’s at risk . As threats, regarding these two risks, Spectre and Meltdown, Fruhlinger wrote, “In the first days of 2018, published research revealed that nearly ever computer chip manufactured in the last 20 years contains fundamental security flaws, with specific variations on those flaws being dubbed Spectre and Meltdown ” (Fruhlinger, Jan 15, 2018). Fruhlinger was stating this: despite the best known efforts Electrical Engineers and Computer Scientists exercised, computer chip technology dated 1998 AD - 2018 AD has experienced an error, design flaws, that led to known defects, Spectre and Meltdown, and these are potentially great failures.  Side-channel technology requires high grade technical research, and this can be because Spectre and Meltdown exist, so a layman would not have known it, 22 years ago. According to Josh Fruhlinger, speculative execution and cac

RISC vs. CISC Architectures: Which one is better?

On January 8, 2018, Scott Thornton wrote RISC vs. CISC Architectures: Which one is better? Thornton stated, “RISC-based machines execute one instruction per clock cycle. CISC machines can have special instructions as well as instructions that take more than one cycle to execute” (Thornton, 2018). Thornton was saying this: between RISC and CISC architectures, the notable difference is instruction timing minus instruction breadth. In contemporary application, the RISC use case is more common because the instruction per-clock-cycle system is a software testing solution. The proof RISC is a software testing solution is software deregulation: Newcastle University School of Computing’s Brian Randall shared insights. Randall wrote, “It was perhaps only when, in 1969, IBM “unbundled” its software by pricing it separately from its hardware that software became a commodity; and a recognisable software industry, and the notion of package software started to come into existence” (Randall, May 201

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