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Utilizing Media: A Response to Deepfakes

  Of the ACM (the Association for Computing Machinery), a magazine called Communication of the ACM's edition releases 1 month before its stated release month. In the latest edition, regarding March 2021, of Communications of the ACM , Column Editor, Susan J. Winter wrote Computing Ethics: What To Do About Deepfakes . Regarding Winter’s desire to halt or hinder illegal or unethical deepfakes, a video technology like wearing a full body masking suit, Winter wrote, “Here are three areas where technical experts can make positive contributions to the development of synthetic media technologies: education and media literacy, subject defense, and verification” (Winter, March, 2021). Winter was saying actions such as teaching and having disruptive technology knowledge, researching professionally, and proving concepts are parts of deepfake experts’ calculus. But this much work specializes such that entry level, junior, work will probably be offered to overqualified professionals. Technic

Utilizing Media: A Response to Deepfakes

  Of the ACM (the Association for Computing Machinery), a magazine called Communication of the ACM's edition releases 1 month before its stated release month. In the latest edition, regarding March 2021, of Communications of the ACM , Column Editor, Susan J. Winter wrote Computing Ethics: What To Do About Deepfakes . Regarding Winter’s desire to halt or hinder illegal or unethical deepfakes, a video technology like wearing a full body masking suit, Winter wrote, “Here are three areas where technical experts can make positive contributions to the development of synthetic media technologies: education and media literacy, subject defense, and verification” (Winter, March, 2021). Winter was saying actions such as teaching and having disruptive technology knowledge, researching professionally, and proving concepts are parts of deepfake experts’ calculus. But this much work specializes such that entry level, junior, work will probably be offered to overqualified professionals. Technic

Of Zero Trust, the Restrictive Drudgery

In recent years, Moore’s Law has begun reaching its limits, and these limits are the sizes of computer hardware. As a history review: when computers were 1st designed, they used vacuum tubes. Through a vacuum tube, this involved an airless vacuum tube meaning ‘0,’ ‘off,’ or air flowing meaning ‘1,’ ‘on.’ In contemporary phones, tablets, and computers, electricity performs this same ‘off’ or ‘on’ task; and with more electric computation devices, but also efficient circuity (electronics components and computation pathways), the more electric computation devices we have, the greater the possible computations. But in size: of the vacuum tube concepts, our common electric versions are reaching the atom’s scale. This is ~1.8E-10: of an approximate average human, it is ~0.00000018% our height. Against Quantum Computing, the basic communication, very much discussed, already, we can discuss another important subject: cyber security. In professional and academic circles, cyber security is not b

On Datapaths: Accepting, but Surpassing Limits

In Computer Organization and Design MIPS Edition, authors, David A. Patterson and John L. Hennessy wrote a piece of information: they defined single-cycle implementation. On single-cycle implementation, Patterson and Hennessy wrote, “Also called single clock cycle implementation. An implementation in which an instruction is executed in one clock cycle. While easy to understand, it is too slow to be practical” (Patterson & Hennessy 2014). Patterson and Hennessy were saying this: for every instruction, an instruction requires one clock cycle. As this is a scalability issue, increasing the instructions to two: requires two clock cycles. Against the pseudo-infinity within, I shall describe, common case hardware, von Neumann computers: this requires a series because this shall make calculation sufficiently easier than a sequence that has no calculation. The series is this: from 0 instructions to n instructions, the series X is incremented one instruction divided the equivalent clock cyc

Data Pipelines and Data Distribution

As the C programming distributive library, MPI (Message Passing Interface), encourages simultaneous application process task because it is efficient enough, our MIPS 5-stage pipeline system allows simultaneous instruction execution. The potential benefit of applying the principles is the sufficient reduction in program execution time. As a major effect, data hazards can occur: when a pipeline changes its read/write accessibility order because the order differ, sequentially; but specifically, on the unpipelined machine, seen regarding sequentially executing instructions[1,2] . Called a data stall because a stall degrades the ideal program performance, the ideal CPI and pipeline stalled-clock cycles per instruction results in a greater than 1 CPI pipelined CPI. For maintaining accurate overhead, cycle time overhead should not be ignored, so pipelining is accurately calculated, but the result will not be an intuitive one. Thankfully, data forwarding can solve data hazards because forwardi

Register Nomenclature and Renaming

On the subjects, registers and register names, scarce information, it seems, regards their origin. However, in August 2020, Siva Nishok Dhanuskodi, Samuel Allen, and Daniel E. Holcomb wrote an article, Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET. Dhanuskodi, et. al., wrote, “Recent works show that subround architectures are especially susceptible to side-channel attacks. In response to this, we extend the register renaming technique to enable microarchitectural randomization of subround AES implementations to mitigate side-channel leakage” (Dhanuskodi, et. al., Aug 2020). For a security purpose, mitigating side-channel attacks, Dhanuskodi, et. al. were saying that they had the validation and verification to rename registers. In this case, the security regarded Advanced Encryption Standard, AES, implementations, a rather powered security protocol.             On 26 June, 2019, ATP Electronics explained the relevance that AES has. ATP E

On Computer Organization and Architecture: the Hierarchy

On study.com, Abirami Thangavel wrote Superscalar & VLIW Architectures: Characteristics, Limitations & Functions. Regarding parallel architectures, superscalar and VLIW, Thangavel wrote: In computer architecture, parallel processing refers to processing of multiple instructions of a program by distributing them among multiple processors. Superscalar and Very Long Instruction Word (VLIW) are parallel architectural models based on Flynn's Taxonomy. Both superscalar and VLIW architectures are capable of executing multiple instructions at one cycle. Each uses a different method for instruction scheduling. While superscalar processors execute instructions dynamically, VLIW uses static scheduling of program instructions.[1] Thangavel was saying this: on Flynn’s Taxonomy, superscalar and VLIW architectures are based, but they have differences. Therefore, on entity priorities, entities have different descriptive capabilities. As follows, a superscalar processor is this: a microproc

On Physical Memory and Virtual Memory: Memory-Resident Malware

Memory Management and Security Abstraction On DifferenceBetween.com, a writer, Indika, wrote Difference Between Physical Memory and Virtual Memory. Indika stated, “Virtual memory allows executing large programs faster when the RAM is not enough" (India, May 19, 2011). I n contemporary times, current 64-bit processors can do this: with 64-bit address buses, they can reference a maximum 2^64 addresses. Even though enough physical memory can be cost-effective; in these systems, this included-physical-memory does not cover the fast or good memory. For reference, a similar Computer Science discipline is Software Engineering. Software Engineering Project Management has three major goals, but a limit, two, shall remain germaine: during a project, these are a good project, a fast project, or a cheap project. Against Software Engineering is Computer Architecture memory management: one component, the physical memory, here, is cost-effective, and it shall either be fast or good. But unlike o

Computer Processors and Human-Computer Interaction

Validating and Verifying Input or Output System Evolution On January 23, 2019, Cris Dar wrote Evolution of Computer Processors. Cris Dar wrote, “Many consider computer processors as the brain of a computing device, but in reality, these tiny little chips are glorified calculators which manipulate the data flow from the software” (Dar, Jan 23, 2019). Dar was saying computer may be called a form of evolution, but their primary prestige is mathematics, and this is even with the following distinction: Computer Science, a CPU’s (Central Processing Unit) professional field basis, being applied mathematics. On mathematics bases, pseudo-limitations allow specialized limits. In IT (Information Technology), these specialized limits may define a media’s utmost functioning capabilities. Further, using correct growth patterns, they can be encouraged. Beyond these constraints, any more performance increases shall be media and non-media asynchronization because human-computer interaction pacing accom

Spectre and Meltdown Explained, and a Proposed Counter Against Them

On January 15, 2018, 2:58 AM PST, Josh Fruhlinger wrote Spectre and Meltdown explained: What they are, how they work, what’s at risk . As threats, regarding these two risks, Spectre and Meltdown, Fruhlinger wrote, “In the first days of 2018, published research revealed that nearly ever computer chip manufactured in the last 20 years contains fundamental security flaws, with specific variations on those flaws being dubbed Spectre and Meltdown ” (Fruhlinger, Jan 15, 2018). Fruhlinger was stating this: despite the best known efforts Electrical Engineers and Computer Scientists exercised, computer chip technology dated 1998 AD - 2018 AD has experienced an error, design flaws, that led to known defects, Spectre and Meltdown, and these are potentially great failures.  Side-channel technology requires high grade technical research, and this can be because Spectre and Meltdown exist, so a layman would not have known it, 22 years ago. According to Josh Fruhlinger, speculative execution and cac

RISC vs. CISC Architectures: Which one is better?

On January 8, 2018, Scott Thornton wrote RISC vs. CISC Architectures: Which one is better? Thornton stated, “RISC-based machines execute one instruction per clock cycle. CISC machines can have special instructions as well as instructions that take more than one cycle to execute” (Thornton, 2018). Thornton was saying this: between RISC and CISC architectures, the notable difference is instruction timing minus instruction breadth. In contemporary application, the RISC use case is more common because the instruction per-clock-cycle system is a software testing solution. The proof RISC is a software testing solution is software deregulation: Newcastle University School of Computing’s Brian Randall shared insights. Randall wrote, “It was perhaps only when, in 1969, IBM “unbundled” its software by pricing it separately from its hardware that software became a commodity; and a recognisable software industry, and the notion of package software started to come into existence” (Randall, May 201

On Trust, Bias, and Privilege: my Response to 'Anti-Blackness is no glitch'

In Winter 2020, Stephanie T. Jones and Natalie Melo wrote ‘Anti-Blackness is no glitch’: The need for critical conversations within computer science education . Jones and Melo mentioned, “The conversation around and application of computer science often reinforces neoliberal ideals” (Jones, Melo, November 25, 2020, pg. 42). Jones and Melo were saying this: the computer science revolution and organizational IT network futuristic left-wing best standards access is telling. For Trust, I am Checking my Privilege But this is not excluding contemporary conversations: any futuristic conversation based on personal interpretation is not from ABBA, so it is not prophecy (NIV, 2 Peter 1:20). For your review, Peter wrote, "For prophecy never had its origin in the human will, but prophets, though human, spoke from [ABBA] as they were carried along by the Holy Spirit" (2 Peter 1:21). You, reader, can predict something shall happen, but prediction is uncertain: it is a terminating series ca

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