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Utilizing Media: A Response to Deepfakes

  Of the ACM (the Association for Computing Machinery), a magazine called Communication of the ACM's edition releases 1 month before its stated release month. In the latest edition, regarding March 2021, of Communications of the ACM , Column Editor, Susan J. Winter wrote Computing Ethics: What To Do About Deepfakes . Regarding Winter’s desire to halt or hinder illegal or unethical deepfakes, a video technology like wearing a full body masking suit, Winter wrote, “Here are three areas where technical experts can make positive contributions to the development of synthetic media technologies: education and media literacy, subject defense, and verification” (Winter, March, 2021). Winter was saying actions such as teaching and having disruptive technology knowledge, researching professionally, and proving concepts are parts of deepfake experts’ calculus. But this much work specializes such that entry level, junior, work will probably be offered to overqualified professionals. Technic
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Of Zero Trust, the Restrictive Drudgery

In recent years, Moore’s Law has begun reaching its limits, and these limits are the sizes of computer hardware. As a history review: when computers were 1st designed, they used vacuum tubes. Through a vacuum tube, this involved an airless vacuum tube meaning ‘0,’ ‘off,’ or air flowing meaning ‘1,’ ‘on.’ In contemporary phones, tablets, and computers, electricity performs this same ‘off’ or ‘on’ task; and with more electric computation devices, but also efficient circuity (electronics components and computation pathways), the more electric computation devices we have, the greater the possible computations. But in size: of the vacuum tube concepts, our common electric versions are reaching the atom’s scale. This is ~1.8E-10: of an approximate average human, it is ~0.00000018% our height. Against Quantum Computing, the basic communication, very much discussed, already, we can discuss another important subject: cyber security. In professional and academic circles, cyber security is not b

On Datapaths: Accepting, but Surpassing Limits

In Computer Organization and Design MIPS Edition, authors, David A. Patterson and John L. Hennessy wrote a piece of information: they defined single-cycle implementation. On single-cycle implementation, Patterson and Hennessy wrote, “Also called single clock cycle implementation. An implementation in which an instruction is executed in one clock cycle. While easy to understand, it is too slow to be practical” (Patterson & Hennessy 2014). Patterson and Hennessy were saying this: for every instruction, an instruction requires one clock cycle. As this is a scalability issue, increasing the instructions to two: requires two clock cycles. Against the pseudo-infinity within, I shall describe, common case hardware, von Neumann computers: this requires a series because this shall make calculation sufficiently easier than a sequence that has no calculation. The series is this: from 0 instructions to n instructions, the series X is incremented one instruction divided the equivalent clock cyc

Data Pipelines and Data Distribution

As the C programming distributive library, MPI (Message Passing Interface), encourages simultaneous application process task because it is efficient enough, our MIPS 5-stage pipeline system allows simultaneous instruction execution. The potential benefit of applying the principles is the sufficient reduction in program execution time. As a major effect, data hazards can occur: when a pipeline changes its read/write accessibility order because the order differ, sequentially; but specifically, on the unpipelined machine, seen regarding sequentially executing instructions[1,2] . Called a data stall because a stall degrades the ideal program performance, the ideal CPI and pipeline stalled-clock cycles per instruction results in a greater than 1 CPI pipelined CPI. For maintaining accurate overhead, cycle time overhead should not be ignored, so pipelining is accurately calculated, but the result will not be an intuitive one. Thankfully, data forwarding can solve data hazards because forwardi

Register Nomenclature and Renaming

On the subjects, registers and register names, scarce information, it seems, regards their origin. However, in August 2020, Siva Nishok Dhanuskodi, Samuel Allen, and Daniel E. Holcomb wrote an article, Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET. Dhanuskodi, et. al., wrote, “Recent works show that subround architectures are especially susceptible to side-channel attacks. In response to this, we extend the register renaming technique to enable microarchitectural randomization of subround AES implementations to mitigate side-channel leakage” (Dhanuskodi, et. al., Aug 2020). For a security purpose, mitigating side-channel attacks, Dhanuskodi, et. al. were saying that they had the validation and verification to rename registers. In this case, the security regarded Advanced Encryption Standard, AES, implementations, a rather powered security protocol.             On 26 June, 2019, ATP Electronics explained the relevance that AES has. ATP E

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